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ATmega128
conversions. For a complete description of this bit, see “The ADC Data Register – ADCL and
ADCH” on page 245 .
? Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See Table 98 for details. If these bits
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 98. Input Channel and Gain Selections
Single Ended
Positive Differential
Negative Differential
MUX4..0
Input
Input
Input
Gain
00000
00001
00010
ADC0
ADC1
ADC2
00011
00100
00101
00110
00111
ADC3
ADC4
ADC5
ADC6
ADC7
N/A
01010
01000 (1)
01001
(1)
01011
01100
01101
01110
01111
10000
10001
ADC0
ADC1
ADC0
ADC1
ADC2
ADC3
ADC2
ADC3
ADC0
ADC1
ADC0
ADC0
ADC0
ADC0
ADC2
ADC2
ADC2
ADC2
ADC1
ADC1
10x
10x
200x
200x
10x
10x
200x
200x
1x
1x
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
N/A
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
ADC4
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC2
ADC2
ADC2
ADC2
ADC2
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
243
2467X–AVR–06/11
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